The present invention relates to a method and/or architecture for implementing programmable frequency modulation generally and, more particularly, to a method and/or architecture for implementing a multi-modulus counter in modulated frequency synthesis.
Referring to FIG. 1, a block diagram of a circuit 10 is shown. The circuit 10 is a conventional modulated frequency synthesizer. The conventional approach employs a loadable counter 12 and an adder 14 in a feedback path of a phase-locked loop (PLL) 16 configured for frequency synthesis. A sum output of the adder 14 is loaded into the counter. 12. The first addend is a base PLL feedback divisor value PB and the second addend is an offset from the base PLL feedback divisor value PO. The offset value PO can be provided from a lookup table 18. The offset value PO can be any integer within the bounds of the adder 14 and counter 12. The total feedback divisor PT is given by the equation PT=PB+PO. The adder 14 is used when the offset values PO are small compared to the base feedback divisor value PB. Supplying an offset instead of a full feedback divisor value reduces the size of the lookup table 18.
Referring to FIG. 2, a block diagram of a circuit 20 is shown. The circuit 20 is similar to the circuit 10 except that a high speed PLL 16xe2x80x2 is employed. The loadable counter 12 can be unable to operate at the speed of a voltage controlled oscillator (VCO) of the PLL 16xe2x80x2. To allow the loadable counter 12 to operate at a lower speed than the PLL 16xe2x80x2, the loadable counter 12 can be preceded by a prescaler 22. The prescaler 22 can be implemented as a fixed divide-by-N circuit, where N is any integer greater than or equal to 2. Because the prescaler 22 precedes the loadable counter 12, the prescaler 22 multiplies the total feedback divisor, resulting in a total feedback divisor equation of PT=N*(PB+PO), or PT=(N*PB)+(N*PO). Because the offset value PO is multiplied by the prescaler value N, the frequency resolution between adjacent PLL feedback divisor values is reduced. Reducing the frequency resolution makes frequency modulation synthesis with the circuit 20 more sensitive to PLL loop gain, hindering performance and resulting in more variation across process and environmental conditions.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a reference input and a feedback signal. The second circuit may be configured to generate the feedback signal according to a plurality of moduli in response to the output signal, a first control signal and a second control signal. The frequency of the output signal may be modulated in response to the second control signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a multi-modulus counter in a modulated frequency synthesizer that may (i) use a multi-modulus counter in place of a fixed prescaler, a loadable counter and an adder to achieve the synthesis of frequency modulation, (ii) use a multi-modulus counter to synthesize a modulation profile, and/or (iii) provide spread spectrum modulated frequency synthesis or clocking.